The present invention relates generally to the electrical, electronic and computer arts, and, more particularly, to forming III-V gate-all-around field effect transistors in integrated circuits with silicon substrates.
Multi-gate field effect transistors (FETs) are of considerable interest because of their superior electrostatic integrity, as well as their promise of lower supply voltages, reduced threshold voltages, and extended scalability. FinFETs are one form of such multi-gate device. In a finFET, a gate typically accesses two or three faces of a channel. However, as the fin width of finFETs approaches five nanometers, channel width variation may cause undesirable variability and mobility loss.
One possible technology that may be able to circumvent this problem is gate-all-around (GAA) FETs. In a GAA FET, a gate is made to surround a channel, which may be structured as a nanowire or a nanosheet (a nanosheet being a nano-sized rectangular cuboid). Such an arrangement provides for the greatest capacitive coupling between the gate and the channel. Incorporating indium gallium arsenide into such GAA FETs may be of particular benefit because of its extremely high electron mobility when compared to silicon, as well as lower operation voltage.
Integrating highly crystalline III-V materials such as indium gallium arsenide with silicon has historically been difficult because of lattice mismatches. One promising technique for effectively growing III-V materials on silicon substrates is Aspect-Ratio Trapping (ART). In an ART-based process, III-V materials are grown on a silicon substrate inside narrow trenches of silicon dioxide. With such techniques, dislocation defects may be significantly reduced or eliminated. Nevertheless, ART processes dictate a specific layout for the III-V devices. Thus the formation of III-V GAA FETs using ART remains challenging.